The present invention relates generally to integrated circuit devices (chips), and more specifically to techniques for coordinating the timing of a microprocessor chip and an external system.
In a personal computer or workstation comprising a microprocessor chip and external (or "off-chip") system components (system logic, memory, peripheral controllers, etc.), timing signals ("clock signals," or simply "clocks") for various parts of the system are typically derived from a single off-chip master oscillator. Computer designers have long recognized that different parts of the system operate at different speeds, and various data buffering, caching, and interrupt strategies have been devised to prevent overall operation speed from being dragged down to that of the slowest subsystem.
While increases in processor speeds have been accompanied by increases (perhaps more modest) in external component speeds, a gap remains. While performance problems relating to mismatches in speed can in principle be minimized by using the fastest components, considerations such as cost and availability may dictate otherwise.